Introduction to Verification and SystemVerilog for Beginners

#6 Module and port declaration in verilog | verilog programming basics | explained with code

Verilog HDL - Installing and Testing Icarus Verilog + GTKWave

verilog code for 4x1 mux with testbench

#4 writing verilog code for different mux ( 4:1, 8:1, 16:1 , 32:1 mux) using conditional operator.

Coding a 4:1 mux using verilog HDL code

Simulating a VHDL/Verilog code using Modelsim SE.

#8 Data flow modeling in verilog | explanation with logic circuit and verilog code

ALU Design in Verilog with Testbench | Simulation in Modelsim | Arithmetic Logic Unit