Electronic Design

Find the Fastest Route to Portable Stimulus Tests with SystemVerilog

Download this article in PDF format. The Portable Stimulus Specification (PSS) is all about reusing commonly used test atoms to create new scenarios more quickly. It saves us from wasting precious ...
Design-Reuse

Transactions in an OVM SystemVerilog Verification Environment

Modeling a verification environment with transactions encompasses many areas, including test bench design and debug, golden model comparison, functional verification between abstraction levels and ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Semiconductor Engineering

Updated UVM Cookbook Supports IEEE 1800.2 Standard And Emulation

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...
Design-Reuse

Functional Finite State Machine Paths Coverage using SystemVerilog

The functional verification process involves the development of constrained random test cases, and the technique of coverage driven verification [1] to produce, and analyze the simulation results.
Electronic Design

Open Verification Methodology Relieves Inefficiencies

Since the IEEE’s adoption of SystemVerilog as IEEE Standard 1800-2005, and EDA vendors’ subsequent release of products supporting that standard, the semiconductor verification teams my company serves ...